This invention relates to a direct digital waveform synthesiser with digital to analog converter (DAC) error correction.
A complete direct digital synthesiser (DDS) generates phase angles, based on a user-defined increment, which are converted to amplitude signals in the form of binary words which are submitted to a DAC to generate an analog output waveform typically in the form of a sine wave. The main xe2x80x9cfigure of meritxe2x80x9d for a complete DDS chip is related to the purity of the sine wave output, and is usually measured as spurious-free dynamic range (SFDR), i.e. the decibel level, below the desired fundamental frequency amplitude, at which the first unwanted frequency occurs in the output spectrum. See Venceslav F. Kroupa xe2x80x9cSynthesis Techniquesxe2x80x9d in xe2x80x9cDirect Digital Frequency Synthesisersxe2x80x9d IEEE Press, N.J., 1999.
Usually, the limiting factor to SFDR performance on such chips is the nonlinearity of the DAC block, which in turn is limited by the analog components which constitute itxe2x80x94usually current source arrays. Digital techniques have been, and continue to be developed to alleviate the DAC accuracy problem, such as xe2x80x9cBarrel shiftingxe2x80x9d, sigma delta, and other techniques. See Rebeschini and Ferguson xe2x80x9cAnalog Circuit Design for Sigma Delta DACSxe2x80x9d in xe2x80x9cDelta Sigma Data Convertersxe2x80x9d, IEEE Press, 1996. These in effect average out the errors over a large number of cycles of the Sinewave. However, the instantaneous error at any time instant is still determined by the DAC performance. Averaging techniques have other shortcomings as well: they require additional current sources and power.
It is therefore a primary object of this invention to provide an improved direct digital waveform synthesiser with digital to analog converter (DAC) error correction.
It is a further object of this invention to provide such an improved direct digital waveform synthesiser with digital to analog converter (DAC) error correction which requires less power and fewer components.
It is a further object of this invention to provide such an improved direct digital waveform synthesiser with digital to analog converter (DAC) error correction which reduces instantaneous error and enables DAC resolution to be extended from ten bits to twelve bits or more and permits a corresponding increase in phase resolution.
The invention results from the realisation that a truly effective, more accurate DDS can be achieved by correcting the error in the DAC by providing to the DAC amplitudes modified to compensate for the non-linear component of the characteristic of the DAC.
This invention features a complete direct digital waveform synthesiser with DAC error correction including a digital to analog converter system for producing a desired output waveform and having between its digital input and analog output a characteristic having a linear component and a non-linear component. There is a phase to amplitude converter including a storage device responsive to phase inputs to provide to the digital to analog converter system amplitudes modified to compensate for the non-linear component of the characteristic of the digital to analog converter system.
In a preferred embodiment the storage device may include a non-volatile memory. The storage device may include an EEPROM. The storage device may include a first storage unit responsive to the phase inputs for storing the modified amplitudes and a second storage unit for loading the modified amplitudes in the first storage unit. The first storage unit may be volatile memory and the second storage unit may be non-volatile memory. The storage device may include an ideal storage unit for storing the ideal amplitudes for a desired output waveform from the digital to analog converter system. There may be an error storage unit for storing the error compensation amplitudes corresponding to the non-linear component of the characteristic and the phase to amplitude converter may further include an arithmetic circuit for combining the ideal amplitudes and error compensation amplitudes to generate the modified amplitudes. The ideal storage unit may provide ideal amplitudes as a binary word. The error storage unit may store the error corresponding to each bit position of the binary word. The phase to amplitude converter may include a detection circuit for detecting which of a predetermined set of the bits of the binary word are set to a logical one and supplying to the arithmetic circuit the amplitude corresponding to each of the bits of the predetermined set of bits set to a logical one. The predetermined set of bits may include all of the bits of the binary word. The storage device may include an ideal storage unit for storing the ideal amplitudes corresponding to the linear component of the characteristic and an error storage unit for storing the error compensation amplitudes corresponding to the non-linear component of the characteristic. The digital to analog converter system may include a primary digital to analog converter responsive to the ideal storage unit for providing an analog output containing the linear and non-linear components and a secondary digital to analog converter responsive to the error storage unit for providing an analog output. There may be a summing circuit for combining the outputs of the primary and secondary digital to analog converters to compensate for the non-linear components.